1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory having storage means connected between word and bit lines.
2. Description of the Background Art
In general, volatile and nonvolatile memories are known as semiconductor memories. A DRAM (dynamic random access memory) is known as the volatile memory, while a flash EEPROM (electrically erasable and programmable read only memory) is known as the nonvolatile memory. The DRAM and the flash EEPROM allowing high integration are widely used.
FIG. 25 is an equivalent circuit diagram showing the structure of each memory cell 103 of a conventional DRAM. FIG. 26 is a sectional view showing the structure of each trench capacitor employed in the conventional DRAM. Referring to FIG. 25, each memory cell 103 of the conventional DRAM, i.e., a conventional volatile memory, is constituted of a selection transistor 101 and a capacitor 102. The capacitor 102 stores information of the memory cell 103 as charges. In order to read the information from the memory cell 103, a word line WL rises to turn on the selection transistor 101. Thus, a cell capacitance Ccell and a bit line capacitance Cb1 are capacitively coupled with each other. Therefore, a bit line potential decided by the quantity of charges stored in the memory cell 103 can be read.
In order to ensure the cell capacitance Ccell of the capacitor 102 also when the memory cell 103 of the conventional DRAM having the aforementioned structure is refined, the trench capacitor formed by vertically extending upper and lower electrodes 102a and 102c and a dielectric film 102b constituting the capacitor 102 is employed as shown in FIG. 26. If refinement further progresses, however, it is difficult to ensure the cell capacitance Ccell of the capacitor 102 with the trench capacitor shown in FIG. 26. In other words, high integration of the DRAM by reduction of a design rule increasingly approaches the limit.
In the flash EEPROM (hereinafter referred to as a flash memory), i.e., the nonvolatile memory, memory cells of a stacked or split gate CHE (channel hot electron) write system are limited in refinement of the channel length. In memory cells of an FN (Fowler-Nordheim) write system such as a NAND form, the limit of refinement is equivalent to that in logic transistors. However, the flash memory requires a high voltage of 15 V to 20 V in operation, and when a power supply voltage for the logic transistors is progressively reduced, generation efficiency for generating the high voltage of 15 V to 20 V from the reduced power supply voltage is reduced. Therefore, power consumption is increased and the area of a charge pumping part is increased, disadvantageously hindering refinement.
On the other hand, a ferroelectric memory is known as one of nonvolatile memories recently watched with interest. This ferroelectric memory utilizes pseudo capacitance variation with the direction of polarization of a ferroelectric substance as a memory element. This ferroelectric memory, allowing data rewriting at a high speed with a low voltage in principle, is spotlighted as an ideal memory having the advantages of the DRAM, i.e., the high speed and the low voltage, and that of the flash memory, i.e., nonvolatility.
Memory cell systems for a ferroelectric memory are roughly classified into three types, i.e., a one-transistor one-capacitor system, a simple matrix system and a one-transistor system. FIG. 27 is an equivalent circuit diagram showing each memory cell 113 of a one-transistor one-capacitor ferroelectric memory. FIG. 28 is an equivalent circuit diagram showing a memory cell array of a simple matrix ferroelectric memory. FIG. 29 is a hysteresis diagram for illustrating operations of the simple matrix ferroelectric memory, and FIG. 30 is a hysteresis diagram for illustrating disturbance in the simple matrix ferroelectric memory. FIG. 31 is an equivalent circuit diagram showing memory cells of a one-transistor ferroelectric memory, and FIG. 32 is a hysteresis diagram for illustrating operations of the one-transistor ferroelectric memory. FIG. 33 is an equivalent circuit diagram for illustrating a voltage application state in writing in the one-transistor ferroelectric memory shown in FIG. 31, and FIG. 34 is an equivalent circuit diagram showing a voltage application state in a standby state of the one-transistor ferroelectric memory shown in FIG. 31.
As shown in FIG. 27, each memory cell 113 of the one-transistor one-capacitor ferroelectric memory is constituted of a selection transistor 111 and a ferroelectric capacitor 112, similarly to a DRAM cell. The memory cell 113 is different from the DRAM cell in the ferroelectric capacitor 112. In operation, a word line WL rises to turn on the selection transistor 111. Thus, a capacitance Ccell of the ferroelectric capacitor 112 and a bit line capacitance Cb1 are connected with each other. Then, a plane line PL is pulse-driven for transmitting charges, varied in quantity with the direction of polarization of the ferroelectric capacitor 112, to a bit line BL. Data is read as the voltage of the bit line BL, similarly to the DRAM cell.
In the one-transistor one-capacitor ferroelectric memory, refinement of the ferroelectric capacitor 112 is limited due to the structure similar to that of the DRAM. Therefore, the one-transistor one-capacitor ferroelectric memory is limited in integration similarly to the DRAM.
The simple matrix ferroelectric memory is now described with reference to FIGS. 28 to 30. As shown in FIG. 28, memory cells 121 of the simple matrix ferroelectric memory are constituted of word lines WL, bit lines BL and ferroelectric capacitors 122 located on the intersections between the word lines WL and the bit lines BL.
First and second ends of the ferroelectric capacitors 122 are connected to the word lines WL and the bit lines BL respectively. This simple matrix ferroelectric memory, reading potentials resulting from capacitive coupling between the bit lines BL and the ferroelectric capacitors 122, must ensure capacitances similarly to the DRAM. However, the simple matrix ferroelectric memory, having the memory cells 121 constituted of only the ferroelectric capacitors 122 with no selection transistors, can be more increased in degree of integration than the one-transistor one-capacitor ferroelectric memory.
Operations of the simple matrix ferroelectric memory are described with reference to FIGS. 28 and 29. Table 1 shows voltages applied to the memory cells 121 in standby, reading and writing states respectively.
TABLE 1StandbyReadWrite “1”Write “0”Selected WL1/2VCCVCC0VCCNonselectedWL1/2VCC1/3VCC2/3VCC1/3VCCSelected BL1/2VCC0→FloatingVCC0NonselectedBL1/2VCC2/3VCC1/3VCC2/3VCC
As to a write operation, both ends of each ferroelectric capacitor 122 are at the same potential in the standby state. In order to write data “0” in any memory cell 121, the ferroelectric memory applies voltages VCC and 0 V to the word line WL and the bit line BL corresponding to this memory cell 121 respectively. At this time, the ferroelectric memory applies the voltage VCC to the ferroelectric capacitor 122 of this memory cell 121. Thus, the ferroelectric memory shifts to a point A shown in FIG. 29. Thereafter the ferroelectric memory sets both ends of the ferroelectric capacitor 122 to the same potential for making a transition to “0” shown in FIG. 29. In order to write data “1” in any memory cell 121, on the other hand, the ferroelectric memory applies the voltages 0 V and VCC to the corresponding word line WL and the corresponding bit line BL respectively. At this time, the ferroelectric memory applies a voltage −VCC to the ferroelectric capacitor 122. Thus, the ferroelectric memory shifts to another point B shown in FIG. 29. Thereafter the ferroelectric memory sets both ends of the ferroelectric capacitor 122 to the same potential for making a transition to “1” shown in FIG. 29.
As to a read operation, the ferroelectric memory precharges the corresponding bit line BL at 0 V. Then, the ferroelectric memory activates the corresponding word line WL to the voltage VCC. Assuming that CFE represents the capacitance of the ferroelectric capacitor 122 and CBL represents the parasitic capacitance of the bit line BL, the voltage VCC is capacitively divided by the parasitic capacitance CFE and the capacitance CBL. The capacitance CFE of the ferroelectric capacitor 122 can be approximated as C0 or C1 in response to data held therein. Therefore, the potential of the bit line BL is expressed as follows:V0={C0/(C0+CBL)}×VCC  (1)V1={C1/(C1+CBL)}×VCC  (2)
The above expression (1) indicates the potential V0 of the bit line BL connected to the memory cell 121 holding data “0”, while the above expression (2) indicates the potential V1 of the bit line BL connected to the memory cell 121 holding data “1”.
A read amplifier determines the difference between the bit line potentials V0 and V1 according to the above expressions (1) and (2) thereby reading data. The data of the memory cell 121 is destroyed in this data reading, and hence the ferroelectric memory performs a write operation (restore operation) responsive to the read data after the data reading.
In the simple matrix ferroelectric memory, data disadvantageously disappear from nonselected cells. More specifically, the ferroelectric memory applies a voltage ⅓ VCC to all nonselected memory cells in writing and reading. As shown in FIG. 30, therefore, the quantity of polarization Q is reduced due to the hysteresis of a ferroelectric substance, leading to disappearance of the data.
The one-transistor ferroelectric memory is now described with reference to FIGS. 31 to 34. As shown in FIG. 31, memory cells 131 of the one-transistor ferroelectric memory are formed by connecting ferroelectric capacitors 132 to gates of MOS transistors 133. In this one-transistor ferroelectric memory, first and second ends of the ferroelectric capacitors 132 are connected to word lines WL and the gates of the MOS transistors 133 constituting cell transistors respectively. In the one-transistor ferroelectric memory, threshold voltages of the MOS transistors 133 vary with the directions of polarization of the ferroelectric capacitors 132, to vary memory cell currents. The ferroelectric memory reads data by determining the variation of the memory cell currents. In the one-transistor ferroelectric memory reading data by detecting the memory cell currents, the capacitances of the ferroelectric capacitors 132 may not be increased to some extent in consideration of bit line capacitances, dissimilarly to the one-transistor one-capacitor ferroelectric memory shown in FIG. 27. Therefore, the ferroelectric capacitors 132 can be so reduced in size that the one-transistor ferroelectric memory is suitable for refinement.
Operations of the one-transistor ferroelectric memory are now described. In a standby state, all word lines WL, all bit lines BL and all source lines SL are at the voltage 0 V. In a write operation for writing data “1” in any memory cell 131, the ferroelectric memory applies a step-up voltage Vpp to the word line WL corresponding to this memory cell 131. At this time, the ferroelectric memory applies a potential VCC capacitively divided with the gate capacitance of the MOS transistor 133 to the ferroelectric capacitor 132. Thus, the ferroelectric memory shifts to a point A shown in FIG. 32 despite the initial state. Thereafter the ferroelectric memory returns the word line WL to the voltage 0 V, for making a transition to data “1” shown in FIG. 32. In order to write data “0” in any memory cell 131, on the other hand, the ferroelectric memory applies the voltage 0 V and the step-up voltage Vpp to the corresponding word line WL and the corresponding bit line BL respectively. In this case, the ferroelectric memory applies a voltage −VCC to the ferroelectric capacitor 132. Thus, the ferroelectric memory shifts to a point B shown in FIG. 32. Thereafter the ferroelectric memory returns the bit line BL to the voltage 0 V, for making a transition to data “0” shown in FIG. 32.
The one-transistor ferroelectric memory performs a read operation by activating the corresponding word line WL to a voltage Vr not causing polarization inversion. Thus, the gate voltage of the cell transistor (MOS transistor) 133 varies with the written state. A current flowing through the cell transistor 133 varies with the gate voltage thereof, and hence the ferroelectric transistor reads the current difference through the corresponding bit line BL. In other words, the one-transistor ferroelectric memory may read not potential difference between the ferroelectric capacitor 132 and the bit line BL resulting from capacitive coupling but the current of the cell transistor 133, to require no polarization inversion in reading. Thus, the one-transistor ferroelectric memory is capable of nondestructive reading.
However, the one-transistor ferroelectric memory has a problem of disturbance of nonselected cells, similarly to the aforementioned simple matrix ferroelectric memory. The one-transistor ferroelectric memory also has a problem of the so-called reverse bias retention of data change resulting from a continuous reverse bias state to the ferroelectric capacitor 132. When the one-transistor ferroelectric memory applies the step-up voltage Vpp to any word line WL thereby writing data in the memory cell 131 corresponding to this word line WL as shown in FIG. 33 and thereafter returns to the standby state, a potential opposite to the direction of polarization is continuously applied as shown in FIG. 34. Therefore, the data holding time is disadvantageously reduced.
A method of reducing disturbance caused in nonselected memory cells of a one-transistor ferroelectric memory is proposed in general, as disclosed in Japanese Patent Laying-Open No. 10-64255 (1998), for example. In a data writing step disclosed in Japanese Patent Laying-Open No. 10-64255, the ferroelectric memory applies voltages +V, ⅓ V, 0 V and ⅔ V to a word line connected to a selected cell, the remaining word lines, a bit line connected to the selected cell and the remaining bit lines respectively as a first procedure. Then, the ferroelectric memory applies voltages 0 V, ⅓ V, ⅓ V and 0 V to the word line connected to the selected cell, the remaining word lines, the bit line connected to the selected cell and the remaining bit lines respectively as a second procedure. If applying voltages −V, −⅓ V, 0 V and −⅔ V to the word line connected to the selected cell, the remaining word lines, the bit line connected to the selected cell and the remaining bit lines respectively in the aforementioned first procedure, the ferroelectric memory applies voltages 0 V, −⅓ V, −⅓ V and 0 V to the word line connected to the selected cell, the remaining word lines, the bit line connected to the selected cell and the remaining bit lines respectively in the second procedure subsequent thereto. Thus, the ferroelectric memory applies voltages ⅓ V of different polarities to most nonselected cells throughout the first and second procedures, whereby disturbance can be remarkably reduced.
In the technique disclosed in the aforementioned Japanese Patent Laying-Open No. 10-64255, however, the ferroelectric memory applies no voltage to those of the non-selected cells sharing the word line and the bit line with the selected cell in the second procedure, and hence these cells are disadvantageously unavoidably disturbed. Further, Japanese Patent Laying-Open No. 10-64255 describes absolutely no method of reducing disturbance in reading.